1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to approaches used to form source/drain regions in a dielectrically isolated FinFET device.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FINFET is formed by the intersection of two shapes, i.e., a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition and etc.
Silicon based FinFETs have been successfully fabricated using conventional MOSFET technology. A typical FinFET is fabricated on a substrate with an overlying insulating layer with a thin ‘fin’ extending from the substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over the fin(s). A double gate is beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow. Other FinFET architectures may include three or more effective gates.
It is currently known that performance improvement in a bulk finFET can be increased by adding high mobility channel materials. Germanium based devices (e.g., Ge-FinFET) include a fin formed at least in part, of germanium (as opposed to a silicon fin). Typical Ge-FinFET fabrication includes patterning a germanium layer on a substrate to form a narrow Ge-fin. However, even high mobility channel materials like Ge have aggravated junction leakage if the device interface is not properly engineered. As shown by the prior art device 10 of FIG. 1, the bulk FinFET suffers from punch-through leakage along the fin channel, which significantly contributes to overall device leakage. Furthermore, prior art device 10 is highly susceptible to damage during punch-through implant, and suffers from carrier spill-out to the undoped fin channel, which lowers the carrier mobility. Accordingly, what is needed is a solution to at least one of these deficiencies.